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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:29:47 08/17/2011 
-- Design Name: 
-- Module Name:    txtest - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

library txtest_lib;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity txtest is
end txtest;

architecture TB of txtest is

COMPONENT MAIN
	PORT(
		Serial_In : IN std_logic;
		Clock_IN : IN std_logic;
		Reset_IN : IN std_logic;          
		Serial_Out : OUT std_logic;
		LED : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;


signal SerialOut_T :  std_logic;
signal CLOCK_T  : std_logic;
signal RESET_T  : std_logic;
signal LED_T : std_logic_vector(7 downto 0);
signal SerialIn_T :  std_logic;

subtype elements is std_logic_vector(9 downto 0);
type bit_array is array (0 to 15) of elements;
signal arr : bit_array ;


begin

arr(0) <= "1101010100"; --AA
arr(1) <= "1101110110"; --BB
arr(2) <= "1000000010"; --01
arr(3) <= "1000000000"; --00
arr(4) <= "1000000000"; --00
arr(5) <= "1000011000"; --0c
arr(6) <= "1000000010"; --01
arr(7) <= "1000000010"; --01
arr(8) <= "1000000100"; --02
arr(9) <= "1100101100"; --96
arr(10) <= "1000000000"; --00
arr(11) <= "1000000000"; --00
arr(12) <= "1000000000"; --00
arr(13) <= "1000000000"; --00
arr(14) <= "1110011000"; --cc
arr(15) <= "1110111010"; --dd

Inst_MAIN: MAIN PORT MAP(
		Serial_Out => SerialOut_T,
		Serial_In => SerialIn_T,
		Clock_IN => Clock_T,
		LED => LED_T,
		Reset_IN => RESET_T
	);
	
	
	RESET_T <= '0';
	
	process
    begin
		CLOCK_T <= '0';
		wait for 10 ns;
		CLOCK_T <= '1';
		wait for 10 ns;
   end process;
	
	
	process
		begin
			SerialIn_T <= '1';
			wait for 100 ns;
--			SerialIn_T <= arr(0)(0);
--			wait for 8610 ns;
--			SerialIn_T <= arr(0)(1);
--			wait for 8610 ns;
--			SerialIn_T <= arr(0)(2);
--			wait for 8610 ns;
--			SerialIn_T <= arr(0)(3);
--			wait for 8610 ns;
--			SerialIn_T <= arr(0)(4);
--			wait for 8610 ns;
--			SerialIn_T <= arr(0)(5);
--			wait for 8610 ns;
--			SerialIn_T <= arr(0)(6);
--			wait for 8610 ns;
--			SerialIn_T <= arr(0)(7);
--			wait for 8610 ns;
--			SerialIn_T <= '1';
--			wait for 8610 ns;
			for j in 0 to 15 loop
				for i in 0 to 9 loop
					SerialIn_T <= arr(j)(i);
					wait for 8610 ns;
				end loop;
--				for i in 0 to 9 loop
--					SerialIn_T <= arr(1)(i);
--					wait for 8610 ns;
--				end loop;
--				for i in 0 to 9 loop
--					SerialIn_T <= arr(2)(i);
--					wait for 8610 ns;
--				end loop;
--				for i in 0 to 9 loop
--					SerialIn_T <= arr(3)(i);
--					wait for 8610 ns;
--				end loop;
			end loop;
	end process;
	

end TB;

------------------------------------------------------------------
configuration CFG_TB of txtest is
    for TB
    end for;
end CFG_TB;
------------------------------------------------------------------